1. Field of the Invention
This invention relates to methods of treatment for semiconductor substrates and in particular, but not exclusively, to methods of depositing a sidewall passivation layer on etched features and methods of etching such features including the passivation method.
2. Description of the Background Art
It is known to etch anisotropically trenches or recesses in silicon using methods which combine etching and deposition. The intention is to generate an anisotropic etch, whilst protecting the sidewalls of the trench or recess formed by laying down a passivation layer.
Such methods are for example shown in U.S. Pat. No. 4,579,623, EP-A-0497023, EP-A-0200951, WO-A-94114187 and U.S. Pat. No. 4,985,114. These all describe either using a mixture of deposition and etching gases or alternate etching and deposition steps. The general perception is that mixing the gases is less effective because the two processes tend to be self cancelling and indeed the prejudice is towards completely alternate steps.
Other approaches are described in EP-A-0383570, U.S. Pat. No. 4,943,344 and U.S. Pat. No. 4,992,136. All of these seek to maintain the substrate at a low temperature and at first, somewhat unusually, use bursts of high energy ions during etching to remove unwanted deposits from the sidewalls.
The continuous trend in semiconductor manufacture is for features of ever increasing aspect ratio, whence the sidewall profile and the surface roughness on the sidewalls, becomes more significant the smaller the width of the feature. Current proposals tend to produce a characteristically notched sidewall with poor CD control, reentrant sidewall profile as well as rough sidewalls and/or bases to the formations and depending on the process being run. The manifestation of these various problems depends on the application and the respective processing requirements; silicon exposed area (unmasked substrate area), etch depth, aspect ratio, sidewall profile, substrate topography.